Processor Design and Function 
This pipelining RISC-V processor is modified based on the single cycle one we did in last lab. Except the added pipelining and hazard handling units, most components remain the same and have been illustrated in last lab report. Here is the list of added pipelining modules and their functions: 
- Hazard Detection Unit o Function: Detect data hazard and stall the PC and pipeline stages. o Assign stall signal when memory read signal is on in ID/EX stage and the destination register is same as source register in IF/ID stage ▪ input IFID_rs1, // IF/ID stage register source 1 ▪ input IFID_rs2, // IF/ID stage register source 2 ▪ input IDEX_rd, // ID/EX stage register destination ▪ input IDEX_MemRead, // ID/EX stage MemRead signal ▪ output logic Stall  
 
- Forward Unit o Function: Handle EX/MEM hazard by forwarding. o Forwarding WB data when destination register in MEM/WB stage is same as register source or ALU result when destination register in EX/MEM stage is same as register source. ▪ input rs1, 
▪ input rs2, ▪ input logic EXMEM_rd, ▪ input logic MEMWB_rd, ▪ input logic EXMEM_RegWrite, ▪ input logic MEMWB_RegWrite, ▪ output logic Forward A, ▪ output logic Forward B 
 
- Src A Mux / Src B Mux o Function: Controlled by Forward Unit to select ALUresult/ RS/ WB-Data to ALU  ▪ input d00, d01, d10, d11 // B.RD, RegWriteData, C.ALUResult, B.RD ▪ input s, // FmuxSel ▪ output y // Fmux_Result 
 
- Pipeline stages for IF/ID, ID/EX, EX/MEM and MEM/WB o Function: Stores signals and resources in registers to keep each stage’s components busy.  
 
- PC flopr o Modified to receive stall signal from Hazard Detection Unit 
 
Synthesis Results: 
(Full synthesis reports are in the Doc or Code/syn folder) 
 
CPU Clock = 1/0.53ns = 1.8868GHz 
 
  Timing Path Group 'clk' 
  ----------------------------------- 
  Levels of Logic:               6.00 
  Critical Path Length:          0.53 
  Critical Path Slack:           1.45 
  Critical Path Clk Period:      5.00 
  Total Negative Slack:          0.00 
  No. of Violating Paths:        0.00 
  Worst Hold Violation:          0.00 
  Total Hold Violation:          0.00 
  No. of Hold Violations:        0.00 
  ----------------------------------- 
 
 
  Cell Count 
  ----------------------------------- 
  Hierarchical Cell Count:          3 
  Hierarchical Port Count:        223 
  Leaf Cell Count:               6053 
  Buf/Inv Cell Count:             473 
  Buf Cell Count:                 190 
  Inv Cell Count:                 283 
  CT Buf/Inv Cell Count:            0 
  Combinational Cell Count:      4675 
  Sequential Cell Count:         1378 
  Macro Count:                      0 
  ----------------------------------- 
 
 
  Area 
  ----------------------------------- 
  Combinational Area:    11251.463223 
  Noncombinational Area:  9109.791976 
  Buf/Inv Area:            823.426559 
  Total Buffer Area:           385.28 
  Total Inverter Area:         438.14 
  Macro/Black Box Area:  50667.683594 
  Net Area:               4846.952980 
  ----------------------------------- 
  Cell Area:             71028.938793 
  Design Area:           75875.891773 
 
 
  Design Rules 
  ----------------------------------- 
  Total Number of Nets:          6203 
  Nets With Violations:             2 
  Max Trans Violations:             0 
  Max Cap Violations:               2 
  ----------------------------------- 
 
  Compile CPU Statistics 
  ----------------------------------------- 
  Resource Sharing:                    3.98 
  Logic Optimization:                  4.30 
  Mapping Optimization:               16.37 
  ----------------------------------------- 
  Overall Compile Time:               58.78 
  Overall Compile Wall Clock Time:    75.50